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LS1028A DIFF_SYSCLK Termination and HCSL Levels

Question asked by Jimmy Meyer on Jun 16, 2020
Latest reply on Jun 16, 2020 by Bulat Karymov

I am in the process of identifying the clock generator ICs to drive the DIFF_SYSCLK receiver and SERDES reference clock on the LS1028A.  I have two concerns.

 

The first is the internal termination for the DIFF_SYSCLK inputs. Figure 10 within the LS1028A shows the termination inside the part (end terminated). The LS1028A Reference Design Board implements termination at the driving clock generator (source terminated). In my research, HCSL is either source OR end terminated, but should not be both. Is there an error in the schematic, or is there no internal termination like shown in Figure 10?

 

The SERDES clock inputs also show 50 Ohm termination inside the part (Figure 44), and the Reference Design Board does not terminate at the source. This would be the correct implementation from my understanding.

 

The second concern is the HCSL voltage levels the LS1028A specifies. The datasheet refers to the SERDES electrical requirements for the DIFF_SYSCLK electrical requirements. In the SERDES electrical requirements in 3.16.2.3, it says the clock should not have a single ended sweep of more than 800mV, and the common-mode voltage should be between 100mV and 400mV. I've looked at several HCSL output parts, and they all have a VOH with 850mV max and a VCM of 250mV to 550mV. This includes the Renasas P49V5907 that was used on the Reference Design Board. Is the LS1028A specification incorrect? Is it safe to use HCSL parts with output voltages that match the Reference Design Board's clock generator? I have yet to find any HCSL parts that match the LS1028A's requirements.

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