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iMX6SX : FECs stop working with PCIe external clock

Question asked by Paolo Minazzi on Jun 11, 2020
Latest reply on Jun 17, 2020 by Yuri Muhin

Dear all,
our board has got an iMX6SX connected to a x86 module by PCIe.

 

  • iMX6SX is a PCIe EP
  • x86 module is a PCIe RC

We have patched uboot-imx6-imx_v2017.03_4.9.88_2.0.0_ga to setup the PCIe EP and this is OK.


We had the PCIe working by getting the PCIe reference clock from the external 100MHz PCIexpress clock.
See also the AN5158 - "PCI Express Certification Guide for the i.MX 6SoloX".
But in this way the FECs stop working because PCIe and FEC clocks are common and FECs clock now is wrong.
Then we searched the forum and the reference manual: we decided to try to clock the FECs from an external 125MHz.
It seems that we did all the necessary but it doesn't work out.

In details:
To have a good and stable PCIe link we have to use the PCIe 100MHz differential ref clock, coming from the PC:
- bypass PLL ENET (set bit16 of CCM_ANALOG_PLL_ENET)
- select CLK1 as bypass source (set bit14, clear bit15 of CCM_ANALOG_PLL_ENET)
- CLK1 becomes an input:
        - clear ANADIG_ANA_MISC1_LVDSCLK1_OBEN (clear bit10 of CCM_ANALOG_MISC1)
        - set ANADIG_ANA_MISC1_LVDSCLK1_IBEN (set bit12 of CCM_ANALOG_MISC1)

This is the code:
reg = readl(&imx_ccm->analog_pll_enet);
reg |= (1<<16);
writel(reg, &imx_ccm->analog_pll_enet);
reg |= (1<<14);
reg &= ~(1<<15);
writel(reg, &imx_ccm->analog_pll_enet);
clrsetbits_le32(&anatop_regs->ana_misc1,
                ANADIG_ANA_MISC1_LVDSCLK1_OBEN |
                ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK,
                ANADIG_ANA_MISC1_LVDSCLK1_IBEN | lvds1_clk_sel);

With these changes PCIe link is OK.

The problem is now that the FECs do not work because the clock is shared with PCIe.
We use two KSZ9031 PHYs, 1GBit.
To solve this problem we try to clock the FECs from a 125MHz coming from the PHY.
Of course, with respect to the evaluation board, the PHYs are not clocked by a 25MHz coming from the iMX: they use their internal oscillator, with a crystal.
In details, the CLK125_NDO pin of the PHY is connected to ENET1_TX_CLK and ENET2_TX_CLK.
And these pads are muxed to ALT1: ENET1_REF_CLK1 and ENET2_REF_CLK2.
The code to get the 125MHz external clock is the following:

imx_iomux_v3_setup_pad(MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 |
                       MUX_PAD_CTRL(ENET_CLK_PAD_CTRL));
imx_iomux_v3_setup_pad(MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 |
                       MUX_PAD_CTRL(ENET_CLK_PAD_CTRL));
clrsetbits_le32(&iomuxc_regs->gpr[1], (1<<17), (1<<13));
clrsetbits_le32(&iomuxc_regs->gpr[1], (1<<18), (1<<14));

Our questions are:

1. Is it possibile to have both
    - an external clock ref for PCIe (100MHz, CLK1p/n pads)
    - an external clock ref for FECs (125MHz) and thus the ethernet working?
2. So, how to provide the 125MHz external clock to the FECs?

3. Internal clock is good for Gen1? or we have to use external clock ?

 

Best regards,

Stefano and Paolo

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