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DDR3 Address Command Routing

Question asked by Ather Shehzad on Jun 10, 2020
Latest reply on Jun 15, 2020 by Ather Shehzad

Sir I am designing a custom board using T1042 and I am using on board DDR3 SDRAMs. While routing DDR3 signals, I am following this document "AN3940-Hardware and Layout Consideration For DDR3".. I am a little bit confused in point 31 in this document i.e.

 

 

Ensure fly-by topology is used for address/command/control and clock groups. The routing in fly-by topology
should go from chip 0 to chip
n and can be in the order that is most convenient for the board design. The
fly-by topology routing of address/command/ control and clock groups must end at the termination resistors
that are after chip
n.
Choose one of the following options to select the impedances and spacings for the DDR3
address/command/control group.
Option #1 (wider traces—lower trace impedance)
• Single-ended impedance = 40
Ω. The lower impedance allows traces to be slightly closer with less
cross-talk.
• Utilize wider traces if stackup allows (7–8 mils)
• Spacing to other like signals = 1.5x to 2.0x
• Spacing to all other non-DDR signals = 3–4x
Option #2 (smaller traces—higher trace impedance)
• Single-ended impedance = 50
Ω.
• Smaller trace widths (5–6 mils) can be used.
• Spacing between like signals should increase to 3x (for 5 mils) or 2.5x (for 6 mils) respectively
• Spacing to all other non-DDR signals = 3–4x with regards to tuning
• Tune signals to +/-10 mils of the clock at each device

In the second option it states that tune signals to +-10 mils of the clock at each device however in the first option it did not say it.

My question is why is it necessary for the signals routed at 50 ohm impedance to length matched and this is not a requirement for 40 ohm impedance signals ?

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