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LPSPI configuration questions regarding the PCS and HREQ

Question asked by salih arslan on Jun 10, 2020
Latest reply on Jun 24, 2020 by Felipe García

Hi, I have a MXRT1052 on a custom board and I need to communicate with AD7175-8 ADCs via SPI. There are four ADCs on the board three of which are connected to LPSPI1 and one of them is connected to LPSPI1. CPU is the SPI master. As stated in the data sheet of AD7175-8, it takes the MISO to low if PCS is zero. I want to use this signal as an interrupt to read data. However, in order to do this PCS pins must be kept low which as far as I understand is not possible with LPSPI functioning. I thought instead of routing those pins to PCSs of SPI, assigning them as GPIO and manually writing to the pins. Since there are more than one slave while communicating with one of them, pins connected to the others must be kept high. My question is if none of the PCS pins are routed to SPI, would there be any problem in SPI functioning?

Also, another question that is it even possible detect an interrupt in SDI pin of SPI module. In reference manual it says that when HRSEL is set to 1, "Host request input is the input trigger", but I am not sure what this means.

Lastly, does SPI in master mode generates clock signal as an output while not communicating?

Thanks in advance.

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