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Android :imx8mn display issue.

Question asked by MOHIT SINGH on Jun 9, 2020
Latest reply on Jun 10, 2020 by igorpadykov

I am trying to boot Android P9.0.0_2.3.4 on our setup which is imx8MN->MIPI->TI sn65dsi83 ->LVDS->Panel.

 

During the inital boot penguins logo comes up fine, however for boot animation I see error "imx_sec_dsim_drv 32e10000.mipi_dsi: clock is not in stop state", as a result Android doesn't come up.

 

Error comes from drivers/gpu/drm/bridge/sec-dsim.c.
The status value is 0x801002f0

/* wait for clk & data lanes to go to stop state */
mdelay(1);

data_lanes_en = (0x1 << dsim->lanes) - 1;
status = dsim_read(dsim, DSIM_STATUS);
if (!(status & STATUS_STOPSTATECLK)) {
dev_err(dsim->dev, "clock is not in stop state\n");
return -EBUSY;
}

 

--------------------------Log at penguins logo ----------------------------------

[ 1.432925] sn65dsi83 0-002c: lvds-channels property not found, using default
[ 1.440122] sn65dsi83 0-002c: failed to parse enable panel gpio
[ 1.500578] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
[ 1.507237] [drm] No driver support for vblank timestamp query.
[ 1.513274] imx-drm display-subsystem: bound imx-lcdif-crtc.0 (ops lcdif_crtc_ops)
[ 1.521164] imx_sec_dsim_drv 32e10000.mipi_dsi: version number is 0x1060200
[ 1.528948] imx-drm display-subsystem: bound 32e10000.mipi_dsi (ops imx_sec_dsim_ops)
[ 1.555248] sn65dsi83 0-002c: DSI clock [ 99000000 ] Hz
[ 1.555255] sn65dsi83 0-002c: Resolution [ 800 x 480 ] Hz
[ 1.556276] sn65dsi83 0-002c: lvds_clk=33000000 lvds_clk_range=0x0
[ 1.557762] sn65dsi83 0-002c: dsi_clk_range=0x13
[ 1.557766] sn65dsi83 0-002c: dsi_clk_div=0x2
[ 1.818311] Console: switching to colour frame buffer device 100x30
[ 1.864749] imx-drm display-subsystem: fb0: frame buffer device
[ 1.871367] [drm] Initialized imx-drm 1.0.0 20120507 for display-subsystem on minor 0

 

 

--------------------------Log at boot animation ----------------------------------

[ 9.922373] init: Received control message 'start' for 'bootanim' from pid: 3061 (/system/bin/surfaceflinger)
[ 9.933134] init: starting service 'bootanim'...
[ 9.939423] type=1400 audit(946685068.128:647): avc: denied { read } for pid=3058 comm="HwBinder:3058_1" name="u:object_r:ffs_prop:s0" dev="tmpfs" ino=2290 scontext=u:r:hal_usb_impl:s0 tcontext=u:objec
t_r:ffs_prop:s0 tclass=file permissive=0
[ 9.961248] type=1400 audit(946685070.252:648): avc: denied { dac_read_search } for pid=1 comm="init" capability=2 scontext=u:r:init:s0 tcontext=u:r:init:s0 tclass=capability permissive=0
[ 11.085185] imx_sec_dsim_drv 32e10000.mipi_dsi: clock is not in stop state
[ 11.092104] imx_sec_dsim_drv 32e10000.mipi_dsi: dsim pll config failed: -16

[ 11.107267] sn65dsi83 0-002c: DSI clock [ 99000000 ] Hz
[ 11.112569] sn65dsi83 0-002c: Resolution [ 800 x 480 ] Hz
[ 11.118988] sn65dsi83 0-002c: lvds_clk=33000000 lvds_clk_range=0x0
[ 11.126694] sn65dsi83 0-002c: dsi_clk_range=0x13
[ 11.131350] sn65dsi83 0-002c: dsi_clk_div=0x2

 

------- relevant device tree entries---------------------------

lcdif: lcd-controller@32E00000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx8mn-lcdif";
reg = <0x0 0x32e00000 0x0 0x10000>;
clocks = <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>,
<&clk IMX8MN_CLK_DISP_AXI_ROOT>,
<&clk IMX8MN_CLK_DISP_APB_ROOT>;
clock-names = "pix", "disp-axi", "disp-apb";
assigned-clocks = <&clk IMX8MN_CLK_DISP_PIXEL>,
<&clk IMX8MN_CLK_DISP_AXI>,
<&clk IMX8MN_CLK_DISP_APB>;
assigned-clock-parents = <&clk IMX8MN_VIDEO_PLL1_OUT>,
<&clk IMX8MN_SYS_PLL2_1000M>,
<&clk IMX8MN_SYS_PLL1_800M>;
assigned-clock-rate = <594000000>, <500000000>, <200000000>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
resets = <&lcdif_resets>;
power-domains = <&dispmix_pd>;
status = "disabled";

lcdif_disp0: port@0 {
reg = <0>;

lcdif_to_dsim: endpoint {
remote-endpoint = <&dsim_from_lcdif>;
};
};
};

mipi_dsi: mipi_dsi@32E10000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx8mn-mipi-dsim";
reg = <0x0 0x32e10000 0x0 0x400>;
clocks = <&clk IMX8MN_CLK_DSI_CORE>,
<&clk IMX8MN_CLK_DSI_PHY_REF>;
clock-names = "cfg", "pll-ref";
assigned-clocks = <&clk IMX8MN_CLK_DSI_CORE>,
<&clk IMX8MN_CLK_DSI_PHY_REF>;
assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>,
<&clk IMX8MN_VIDEO_PLL1_OUT>;
assigned-clock-rates = <266000000>, <594000000>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
resets = <&mipi_dsi_resets>;
power-domains = <&mipi_pd>;
status = "disabled";

port@0 {
dsim_from_lcdif: endpoint {
remote-endpoint = <&lcdif_to_dsim>;
};
};
};

 

 

cheers,

mohit

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