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DDR Access from M4 when A7 is in VLLS (IMX7ULP)

Question asked by Vivek Rajpara on Jun 5, 2020
Latest reply on Jun 10, 2020 by Vivek Rajpara



In our setup, we want to put A7 in very low power mode but at the same time, we want to access DDR from the Cortex M4. 


The main reason for this design to have around 10MB available with M4.


Can anyone please let us know if this is possible or not, it is a deciding factor for our solution, looking forward to quick confirmation on this fact, also if possible, it would be great if someone can share some sample or document explaining process for performing such operations.