There is an issue with MPC555 code or my hardware that I am investigating. I am using a debugger to find the issue.
The issue happens only at cold temperature, most probably one of the components upset.
By debugger I can see DAR register address gets corrupted out of range and so MCU stops execution.
Using the debugger I do not have a clue why this happens because by this debugger I can not go back in the code and do a lot of tracing. The assembly line where debugger stops is: lfs f28,0x5C(r12)
It seems MCU is trying to access an address in the SRAM located at (0x5C+r12), but because r12 is out of range, MCU stops.
The only anomaly I see using the debugger is DAR register which is set to (0x5C+r12) and is out of range.
DAR definition in MPC555 datasheet: After an alignment exception, the DAR is set to the effective address of a load or store element.
I am still scratching my head how this address corruption happens. So I need some help from an expert.
In the HW I have ADDR[8-31] pins and DATA[0-31] shared between my 3 peripherals that are SRAM, FLASH and a Digital Transceiver.
How the value in DAR is relevant with ADDR[8-31]. Is it possible that that when r12 data is being passed on data bus it gets corrupted due to a timing issue by one of the other devices?