I have been investigating a CPU stall issue with my project. I realized that the number of instruction completed in a second (number retreived thanks to PMCs) is higher when I disable the L2 cache.
My tests only uses one core and the second core is disabled.
When L2 cache is disabled, I get 1.25x more instruction completed in a second. The CPI is still low (more than 2) but is better than with L2 enabled.
Can this issue be related to clock settings? If not do you have any idea to investigte the issue?
EDIT: I would like to add that my CPI is between 10 and 20m which is terrible. I think is is linked to this issue, but maybe there is an underlying cause.