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PCIe Clocks

Question asked by Bryan Neperud on May 28, 2020
Latest reply on May 29, 2020 by Bryan Neperud

We are trying to get PCIe working with Linux on a custom board with an i.MX6Q and an external PCI clock generator, using the linux-imx_4.19.35 Yocto warrior kernel.

 

I've seen Setting the iMX6 PCIe Clocks and other posts saying the 100 MHz SATA clock must be enabled to access PCIe registers, but my experience seems to indicate the opposite:

  • With CCM_ANALOG_PLL_ENET bit 20 (ENABLE_100M) set to enable the SATA clock, the kernel hangs when it first tries to access PCI registers (specifically, when it goes to read MPLL_OVRD_IN_LO in setting up for the external clock).
  • With CCM_ANALOG_PLL_ENET bit 19 (ENABLE_125M) set instead (bit 20 is 0), the kernel is able to access PCI registers, we end up with the "phy link never came up" message instead.

 

In other words, what we see is that PCI register access requires the 125M PCIE clock be enabled, but the community says PCI register access requires the 100M SATA clock be enabled. Any ideas to explain the difference?

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