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iMX6 Quad Local Timer

Question asked by Ken Green on May 25, 2020
Latest reply on May 25, 2020 by Yuri Muhin

I want to use the local timer in one of the cores to create a "tick" timer. According to what I've read in various manuals, each of the cores in the iMX6 Quad has a private timer that can be used for my application. My understanding is that each of these timers will have the same bus address (for ease of SW)  but the timer will only respond to the core it belongs to; kind of like a private address within the core.

 

My problem is that there is not a lot of information about these timers. I believe that the address of the timer starts at 0x00A00600 - is this correct? I believe the register structure is:  


// LOCTMR - Peripheral register structure
typedef struct LOCTMR_MemMap
{
   uint32_t LDVAL;               //counter reload value      offset 0x000
   uint32_t CNTR;                //count reg                 offset 0x004
   uint32_t CNTL;                //control reg               offset 0x008
   uint32_t INTSTS;              //interrupt status reg      offset 0x00C
} volatile *LOCTMR_MemMapPtr;

 

Is the above information correct? I have been unable to find what the interrupt vector is - where do I find it?

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