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A7/M4 timing issue using power_mode_switch example

Question asked by Guillaume Audirac Employee on May 22, 2020
Latest reply on May 26, 2020 by Guillaume Audirac



My use case: when A7 goes to VLLS, switch M4 to VLLS and wait for an event (GPIO or LPTMR) to wake up, then wake up A7 too.


Platform: 7ULP EVK
7ULP: any default image (using core-image-base)


From the power_mode_switch example, I have simplified the task PowerModeSwitchTask() to switch the M4 to VLLS power state as soon as the A7 is itself in VLLS mode. However, in this situation, the M4 goes into VLLS prior to seeing the message "CA7 in VLLS status, power off unused regulator!", which means before the peer core is in 'deactivating' state.
As a result, the wake up never happens, whatever the selected mode to trigger it (GPIO/VOL+ or LPTMR). The only workaround being to add a 1 second delay after the CA7 is detected to be in VLLS state. This timing issue should have another robust option to solve it, do you know how?

And by the way, is there a potential issue in the example within the state machine of the APP_SRTM_PollSuspend() function?


I attached the two modified files from the power_mode_switch project for simple testing.
CA7 can be switched to VLLS with:

# echo "mem" > /sys/power/state

By default, GPIO event is selected (see TODO tag) and the extra delay workaround has been commented out (see FIXME tag).