How to use external crystal of MC56F82748?Is there anything wrong with the configuration?

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

How to use external crystal of MC56F82748?Is there anything wrong with the configuration?

Jump to solution
679 Views
547351265
Contributor II

1. When the recommended crystal oscillator is changed to 12M or 16M,Are they(R5 R7 R6 C5 C6 ) still the values in the picture? 

无标题.png

2. The above program is configured by imagek.
配置图片.png

3.Is there anything wrong with the configuration? What went wrong with the program?Procedure is as follows

 SIM_PCR=0X0400;
 SIM_PCE0=0X0010;
 SIM_GPSCL=0X00C1;
 SIM_MISC0=0X0002;
 
 SIM_CTRL=0X00C0;
 SIM_MSHID=0X0980;
 SIM_LSHID=0X001D;
    SIM_IOSAHI=0X0000;
    SIM_IOSALO=0X0380;
    SIM_NVMOPT2H=0X0220;
    SIM_NVMOPT2L=0X7100;
   
 INTC_IPR1=0X0000;
 GPIOC_PUR=0X0003;
 GPIOC_PER=0X000B;//0X0003;
 GPIOC_DDR=0X0000;
 OCCS_CTRL=0X0085;
 OCCS_DIVBY=0X2113;
 OCCS_STAT=0X0000;
 OCCS_OSCTL1=0X2220;
 OCCS_OSCTL2=0X8100;
 OCCS_CLKCHKR=0X0000;
 OCCS_CLKCHKT=0X0000;
 OCCS_PROT =0X0000;
/** for test system clock **/
    //GPIOC2, TXD0, XB_OUT11, XB_IN2, CLKO0
    //1)enable gated clock
    SIM_PCE0|=1<<4;
    //2)pin assignment for CLKO0
    //set the peripheral register so that the pin of GPIOC2 is set up as peripheral
    GPIOC_PER|=1<<2;
    //select the pin
    SIM_GPSCL|=3<<4; //set the C2 bits
    //3)enable CLKO0 clock
    SIM_CLKOUT=0xE000;
Tags (1)
0 Kudos
1 Solution
630 Views
xiangjun_rong
NXP TechSupport
NXP TechSupport

Hi, HZ Zhang,

First of all, regarding the C5/C6/R6, I think it is dependent on the crystal manufacturer specs, anyway, I think they are required. For the R5/R7, I do not think they are required.

I attach the OCCS module diagram, if the external crystal is 12MHz, the OCCS_DIVBY=0x2113, PLLDB=0x13, COD =0x01

the Fpll frequency=12MHz*(0x13+1)=12*20=240MHz.

Fpll/2 frequency is 120MHz.

SYS_CLK_2x=120MHz/(COD+1)=60MHz.

The SYS_CLK=SYS_CLK_2x/2=30MHz.

so the above configuration is correct.

Hope it can help you

BR

XiangJun rong

pastedImage_1.png

View solution in original post

0 Kudos
1 Reply
631 Views
xiangjun_rong
NXP TechSupport
NXP TechSupport

Hi, HZ Zhang,

First of all, regarding the C5/C6/R6, I think it is dependent on the crystal manufacturer specs, anyway, I think they are required. For the R5/R7, I do not think they are required.

I attach the OCCS module diagram, if the external crystal is 12MHz, the OCCS_DIVBY=0x2113, PLLDB=0x13, COD =0x01

the Fpll frequency=12MHz*(0x13+1)=12*20=240MHz.

Fpll/2 frequency is 120MHz.

SYS_CLK_2x=120MHz/(COD+1)=60MHz.

The SYS_CLK=SYS_CLK_2x/2=30MHz.

so the above configuration is correct.

Hope it can help you

BR

XiangJun rong

pastedImage_1.png

0 Kudos