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iMX8QXP Bare metal Cortex m4 cache initialization

Question asked by David Binet on May 20, 2020
Latest reply on Jun 17, 2020 by David Binet

Hi, 

 

I'm currently working on a baremetal application on the M4 inside the i.MX8QXP and I'm having issues activating the cache. I would like to make sure I'm not missing any steps. I based my configuration of the MPU and cache on the  configuration found in FreeRTOS_BSP_1.0.1_IMX7D. The application code and data are in DDR at 0x8000_0000. Here are the configuration steps:

 

  1. Configure MPU:
    1. Disable MPU in MPU CTRL (bit enable)
    2. Select region 0 with RNR
    3. Configure base address 0x8000_0000 in RBAR
    4. Apply the following configuration in RASR (0x030B003D):
      1. Enable Instruction Access;
      2. Full Data Access Permission;
      3. Write Back, Write Allocate;
      4. Region Not Shared;
      5. All Sub-Region Enable;
      6. MPU Protection Region size = 2GB;
      7. Enable Region 0.
    5. Enable MPU in MPU CTRL (bit enable)
    6. dsb/isb
  2. Enable cache in CCR
    1. Write 0x8500_0003 to CCR based on section 12.2.5.3.6.1 Cache set commands of IMX8DQXP reference manual. I noticed that this step was not in FreeRTOS for the iMX7. Is it normal ?
  3.  Configure PSCCR
    1. Set invw1 and invw0 in PSCCR register
    2. Set go in PSCCR 
    3. I noticed that the bit go is never set back to 0 as expected in FreeRTOS code.
    4. Set ENWRBUF and enable in PSCCR
  4. Configure PCCCR
    1. Set invw1 and invw0 in PCCCR register
    2. Set go in PCCCR 
    3. I noticed that the bit go is never set back to 0 as expected in FreeRTOS code.
    4. Set ENWRBUF and enable in PCCCR

Is there any steps that I'm missing to enable the cache properly ? If you need any more information please feel free to ask.

 

Thanks for your support,

 

David

 

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