my development board is IMX7DSABRE. Linux kernel version is 4.9.88
When I use the EIM bus to communicate with the FPGA, I use asynchronous 16-bit data lines and 27 address lines for communication. After reading the manual, I found that the asynchronous access method does not require the EIM_BCLK clock. But I also saw the description of EIM clk cycle in the IMX7DRM manual. For example, EIM_CSnGCR2 [7-4] -DAPS: 0010 5 EIM clk cycles between start of access and first DTACK check etc.
Question 1: I want to know what is the EIM clk cycles here? According to which register is it configured?
Question 2: I measured the clock frequency of my EIM_BCLK to be 120MHz. I changed the value of the BCD field of the EIM_CSnGCR1 register. I went to measure and found that it was still 120MHz. Why is this?
My EIM register configuration is as follows:
Register: CSxGCR1 CSxGCR2 CSxRCR1 CSxRCR2 CSxWCR1 CSxWCR2
Address: 0x30bc0000 0x30bc0004 0x30bc0008 0x30bc000c 0x30bc0010 0x30bc0014
Value: 0x00613081 0x00000001 0x1c022000 0x0000c000 0x1404a38e 0x00000000