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How to config MIPI DSI clock and data rate on imx8mq?

Question asked by CS Lin on May 18, 2020
Latest reply on Jun 22, 2020 by Joan Xie

hi all:

Now we are porting a 5" LCM on imx8mq playform with LCDIF. we got panel timing data as below, and vendor stated that is base on mipi bit rate 540MHz

display-timings {
      timing {
         clock-frequency = <63000000>;
         hactive = <720>;
         vactive = <1280>;
         hfront-porch = <12>;
         hsync-len = <12>;
         hback-porch = <24>;
         vfront-porch = <10>;
         vsync-len = <20>;
         vback-porch = <20>;
         hsync-active = <0>;
         vsync-active = <0>;
         de-active = <0>;
         pixelclk-active = <0>;
   };
};

After we apply this timing config, we can't see nothing on panel. Vendor request us to change MIPI DSI clock and data rate to meet 540MHz base, so how can I make it? Please help advise the details.

I found below setting in Nwl-dsi.c. Is it what I am looking for? I can change it randomly? or any rule to calculate these values?

/* Possible valid PHY reference clock rates*/
static u32 phyref_rates[] = {
         27000000,
         25000000,
         24000000,
};

 

Also, in Fsl-imx8mq.dtsi, we have below

mipi_dsi_bridge: mipi_dsi_bridge@30A00000 {
               #address-cells = <1>;
               #size-cells = <0>;
               compatible = "nwl,mipi-dsi";
               reg = <0x0 0x30A00000 0x0 0x400>;
               interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
               clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>,
                              <&clk IMX8MQ_CLK_DSI_AHB>,
                              <&clk IMX8MQ_CLK_DSI_IPG_DIV>,
                              <&clk IMX8MQ_VIDEO_PLL1>;
               clock-names = "phy_ref", "rx_esc", "tx_esc", "video_pll";
               assigned-clocks = <&clk IMX8MQ_CLK_DSI_AHB>;
               assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
               assigned-clock-rates = <80000000>;
               phys = <&mipi_dsi_phy>;
               phy-names = "dphy";
               no_clk_reset;
               status = "disabled";

               port@0 {
               mipi_dsi_bridge_in: endpoint {
                        remote-endpoint = <&mipi_dsi_out>;
               };
   };
};

Or I should modify these clock config to meet mipi dsi data rate and clock I need? (540MHz). I can find indevalues of these clock definition, but ow can I map these clock definition to real valuse? Please help advise, thanks!!

 

thanks

CS

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