I made a boundaryscan project for a board with a Vybrid module MVF50NS151CMK40 using the "Cascon" tools from Göpel electronic.
I have a bad answer when I read the ID register:
Cascon tools reads 0100 1011101000000000 01000111011 1 (4BA00477).
Value expected (see BSDL): 0001 1001100000000000 00000001110 1 (1A80001D).
The value reads (4BA00477) is the "debug ID code from the JTAG DP port" (see sheet 1286 of the VFXXX controller reference manual).
So, I understand that the Vybrid is in debug mode, not in test mode (JTAG 1149.1).
In the BSDL (VYBRID_364_F.bsdl), there is no compliant pattern or design warning.
Is there a special configuration to work with the "test" tap port, based on IEEE1149.1 specification ?