S9KEAZN64 internal clock configuration

Hi,

I will reply you immediately .

Jianyu: 

Have a great day,
TIC

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Hi,

I do know that KEAZN64 has 1024 times the internal .   And from the datasheet, it shows internal clock from 31.25k-39.0625k. The typical value is 31.25k. This value is calibrated by factory .So we need to wite a new trim to ICS-c3.So could you please write ICS_CS =0; Please have a try.

Jianyu: 

Have a great day,
TIC

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Hi,

From the reference manual,KEA64 support  S9KEAZN64.

And internal clocking sources is from  31.25-39.0625khz. Which clock do you need to be 40khz.

Refer this demo ,

change the internal clock to 31.25 by config ICS_C3,core clock is 40mhz, bus clock is20Mhz.

change uart2 to uart0. and change BDL to 11. The baud rate as shows in follow pic .

Please have a try.

Jianyu: 

Have a great day,
TIC

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Hi,

You can refer uart (FEI bus 20M baud 115200)code in "SDK-DRIVER-FRDM-KEA-S32DS\KEAZ64 Driver testcode and Examples (for S32DS)\FRDM-KEAZ64_Driver Testcodethis code" ,you can get it from attach file.

Jianyu: 

Have a great day,
TIC

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Hi,

Code as follows,please have a try

void Clk_Init(void)
{
    ICS_C1=0x4;         /* Enable the internal reference clock*/
    ICS_C3= 0x90;                        /* Reference clock frequency = 39.0625 KHz*/        
    while(!(ICS_S & ICS_S_LOCK_MASK));   /* Wait for FLL lock, now running at 40 MHz (1024 * 39.0625Khz) */        
    ICS_C2|=ICS_C2_BDIV(1)  ;             /*BDIV=2, Bus clock = 20 MHz*/
    ICS_S |= ICS_S_LOCK_MASK ;             /* Clear Loss of lock sticky bit */        
}

Jianyu: 

Have a great day,
TIC

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