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i.MX RT106x SEMC address alignment for external SRAM

Question asked by Nick Wallis on May 14, 2020
Latest reply on May 14, 2020 by jeremyzhou



We are using MIMXRT1062DVJ6A with external SRAM memory (Cypress # CY7C1051DV33-10ZSXI), this memory is 512k x 16, we have two of them (on different chip selects), the external databus is x16. The SEMC is in ADMUX mode.


Does anybody know the address alignment when using the SEMC in this mode? I think it is x16 aligned, and so A1 from the MCU goes to A0 on the SRAM, etc..... (A0 from the MCU is not used).


Does anybody know for sure? The reference manual does not have much information on this.


thanks and regards

Nick Wallis