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SPC5675KFF0MMS2:The RESET always keep low level in up-down power test

Question asked by Tom Gao on May 14, 2020
Latest reply on May 25, 2020 by Lukas Zadrapa


The MCU will not operate normally during the up-down power test. Our circuit is shown in the following figure

PS:RESETn is Y2 Pin



The RESETn and JCOMP  pins of MCU are pulled up to 3.3V  through the resistance, and connected to RST through a diode respectively. RST is connected to the external hardware watchdog . We do the circuit board up and down power test, the test times are 1000 times, and MCU cannot operate normally twice. At this point, the RST is pull up to 3.3V by an external circuit. At this point, the measurement RESETn is low (abnormal), Jcomp is high (normal), and the connection debugger cannot be connected normally. Circuit board power on again, the MCU can operate normally.



RESETn as an input pin, under what circumstances will it be lower?

Whether the fault will disappear after the power is recharged?