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CFG_SHIFT_MODE usage in PCIe block on iMX8M

Question asked by Neil Shipp on May 13, 2020
Latest reply on Jun 25, 2020 by jamesbone
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In the iMX8MQ PCIe IP block, by default, the config space is laid out using a B:D:F format of B[31:24]:D[23:19]:F[18:16] when using the ATU to map the config space.  This differs from B[27:20]:D[19:15]:F[14:12] specified in table 7-1 of the PCIe 4.0r0.7 base standard.
In the iMX8MQ documentation, there is a CFG_SHIFT_MODE bit specified in the iATU Region Control 2 Register which is documented as follows:
CFG Shift Mode. The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP. This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space. Note: This register field is sticky.
This appears to change the config memory layout to reflect the PCIe standard. However, when I enable this bit to read the CFG1 address space, I cannot find any device config structures mapped into the expected address ranges.  Are there any other registers that are required to be configured to enable this feature?  Is there any guidance on using this on the iMX8MQuad and iMX8M Mini?  The iMX6SoloX errata sheet mentions it doesn't work correctly on that platform.  I've looked at the Linux DesignWare PCIe driver source code and it doesn't define or use this bit.
I want to map the entirety of the CFG1 address space for 8 buses into an 8MB address block using a static ATU entry instead of having to dynamically update an ATU element each time I want to address a different device or bus.

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