Hi community, I am learning fresh about the I.MX8 on my MCIMX8QXP-CPU development board. I have been getting fairly acquainted with the Yocto build and such. I have so far successfully added my own layer where I can run a user-space program on this dev board as well as insert a "hello" Linux module which auto-loads upon boot. So I'm in the first phases of this journey of I.MX8 support.
I suppose no easy way to ask this, but the question about how to map the pins to certain functions is one that eludes me at this time. I have watched some material about DTS files, but not sure if this is exactly what I need to look at. Either way, I would eventually like to understand how pin X is configured by default to serve as say a GP Output, or a SPI RX line, etc. It is not clear to me how one is supposed to easily support the I.MX8 if you are not aware of what pins have in terms of functions that can be multiplexed to them.
And another thing that eludes me is how to configure a peripheral - such as SPI or UART... How does the kernel know how to set the baud rate correctly for a UART? I know from my experience, I would read a micro-controller's reference manual and write the correct value to a specific register associated with the UART. Or like a SPI bus, how to set the clock speed, clock polarity/phase... how does the kernel know how to do these things in general to peripherals that I know have to have some register at some memory mapped address that operates based on what value is present in these registers?
So pins and their functions is of interest to me - any links that spell these out to me would be great. How are peripherals set up as well would be where I would want to go next, but I suppose first things first. This question is mainly about understanding how the kernel maps out the pins to particular functions.
Thanks in advance. I am working hard to figure all this out. I am relatively new to Linux and the I.MX family, so please forgive me for my lack of "basic" knowledge here. I appreciate any helpful feedback I receive.