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Problem with Flextimer's quadrature decoder mode on IMX7S

Question asked by James Jamesson on May 8, 2020
Latest reply on May 13, 2020 by James Jamesson

Hi, Community,

 

I am experiencing problems with using the Flextimer in the quadrature decoder more, as the counter stops incrementing as soon as I enable QUADEN in QDCTRL register. I am using the following initialization scheme:

 

// All registers using default values up to this point
FTM2_SC &= ~FTM_SC_CLKS_MASK;
FTM2_MODE |= FTM_MODE_FTMEN_MASK;
FTM2_MOD = 1000;
FTM2_CNTIN = 100;
FTM2_CNT = 0;
FTM2_SC |= FTM_SC_CLKS(1);
FTM2_QDCTRL |= FTM_QDCTRL_QUADEN_MASK;
while(1) {
   debug(("FTM2_CNT value: %5d\n\r", FTM2_CNT));
}

 

Notes:

1) The counter value will reach 113 and stop increasing due to enabling QUADEN.

2) I have initialized clocks for FTM2 (RDC = 37, ROOT = 111(0x3038b780), CCGR = 129(0x30384810))

3) I have initialized clocks for the PHA and PHB pins (SAI1 port, RDC = 106, ROOT = 74(0x3038a500), CCGR = 140(0x303848c0))

4) I am using ALT4 for MUX-ing both the PHA (SAI1_RXC) and PHB (SAI1_MCLK) pins

5) Regularly reading the PHA and PHB pins as GPIOs works correctly

6) I am aware that the IMX7S datasheet has incorrect bit numeration in the datasheet's FTM register parts, so I have used K64 datasheet's register numeration instead when declaring the bitmasks.

7) I have tried various ways of initialization orders without any results

8) I have validated with an oscilloscope that the encoder signals are valid

 

I have read the datasheet multiple times and have read all forum posts and documents there are on this topic, so I'm hoping that you can point out something that is wrong for me.

 

With regards,

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