we would like to write an error message into flash after the watchdog fires an interrupt.
The Real Time Watchdog offers a backup reset functionality but the time after the interrupt is limited to 255 cycles of the bus clock.
1. Is it really limited to the bus clock? Is the bus clock the ipg_clk_root? If ipg_clk_root is 99 MHz this would mean that there are only 2,58 us which is too short for writing into flash.
The WDOG1 peripheral does not provide a backup reset description. Assume it is clocked from 32kHz LPO.
2. If the Core clock stops will the WDOG1 interrupt still be fired and will the WDOG1 peripheral reset the system after timeout? Or does the WDOG1 not work anymore after the Core clock is stopped?