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iMX28 / FEC: ethernet link breaks on MAC reset

Question asked by Laurent Badel on Apr 29, 2020
Latest reply on May 3, 2020 by Yuri Muhin

I'm encountering issues with an iMX28 connected to a LAN8720 PHY chip on a board very similar in design to the MX28-EVK. 

 

The symptom of the issue is the swinging ethernet link which has been discussed in many threads already. The generally accepted solution is to reset the PHY chip after enabling the ENET clock, but this doesn't seem to work on recent linux kernels (using v2.6.35 distributed by NXP, I am able to fix the issue by bringing the PHY into reset before bringing the interface up, and holding the reset until the interface is up, but this doesn't seem possible in recent kernel probably due to modifications in the generic phy driver - using the SMSC driver doesn't work either as the PHY needs to be up for probing during fec_enet_open()).

 

What I've found is that the problem can be (seemingly) fixed by issuing a soft- instead of a hard-reset in fec_restart(), which is called as soon as the link is detected to be up. That is, replace at what is now line 965 of fec_main.c > fec_restart()

writel(1, fep->hwp + FEC_ECNTRL);

by

writel(0, fep->hwp + FEC_ECNTRL);

I've tried very hard to find a solution that doesn't involve changing the reset but this is so far the only fix that worked for me (and it does seem to work very reliably). 

 

Right now I suspect that the hard reset might disable the clock for a few cycles and that's what might be causing the link to break. In support of this, I can recreate the issue by quickly disabling and re-enabling the clock after the soft-reset

writel(0, fep->hwp + FEC_ECNTRL);
clk_disable(fep->clk_enet_out);
clk_enable(fep->clk_enet_out);

 

Is this the intended behavior or a known issue? Might there be a different way to get around it? 

 

Thanks in advance for your answers,

 

Laurent Badel

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