I am working on RT600 dev board (ekvmimxrt685). I've successfully evaluated the demo program of MU (inter core communication). Then I intend to evaluate inter core communication through the shared memory.
The very basic thing I intended to do is: DSP writes a value to a position. (such as put 0x12345678 to address 0x40000). Then MCU checks if it can see 0x12345678 at address 0x40000.
I found MCU could ONLY see the data that DSP writes at 0x24000000 (TCM) space.
Then I know cache matters. And I have the following lines (in the DSP's program) before this "writng data" test:
/* Disable DSP cache for noncacheable sections. */
(uint32_t)&NonCacheable_end - (uint32_t)&NonCacheable_start, XCHAL_CA_BYPASS, 0);
(uint32_t)&NonCacheable_init_end - (uint32_t)&NonCacheable_init_start, XCHAL_CA_BYPASS,
But it made me really confused, even space 0x20040000 (and following 256kbyte) are set to uncached, I still could not let MCU see DSP's writing data at 0x20040000.
Looking forward to have some support from this forum.