i.MX8QM HDMI to out display

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i.MX8QM HDMI to out display

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lizboxy
Contributor I

1)下载官方L4.14.98_2.0.0_ga_images_MX8QMMEK中的fsl-image-validation-imx-imx8qmmek.sdcard下载自己设计的电路板中HDMI没有显示,请教这个镜像本身是支持HDMI显示吗,或者需要uboot启动后设置HDMI显示环境变量。

下载文件方法是:自己制作flash.bin,然后使用命令:uuu -b emmc_all flash.bin fsl-image-validation-imx-imx8qmmek.sdcard

2)如果默认镜像不支持HDMI显示,主要修改那些地方?

3fsl-image-validation-imx-imx8qmmek.sdcard这个文件可以用已经编译好的内核和设备树替换生成吗?

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joanxie
NXP TechSupport
NXP TechSupport

i.mx8qm supports dual channel lvds, you can use imx8qm-mek-jdi-wuxga-lvds1-panel.dtb to support this panel, if you use this panel, you can set dtb file as imx8qm-mek-jdi-wuxga-lvds1-panel.dtb, the dual channel is like this:

pastedImage_1.png

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2,173 Views
lizboxy
Contributor I

And any driver for the EDP 9" panel with 1536x2048-25Hz?

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2,173 Views
joanxie
NXP TechSupport
NXP TechSupport

current bsp doesn't has this, customers need to porting by themselves

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2,173 Views
joanxie
NXP TechSupport
NXP TechSupport

1)yes, which port do you use? you can use mipi lvds port with LVDS to HDMI converter board or mipi dsi port with MIPI-DSI to HDMI converter board

3you can built your own sd card image, pls refer to the sd card layout link as below, but I suggest that you can download image to your board by uuu separately

"meta-fsl-arm/image_types_fsl.bbclass at master · Freescale/meta-fsl-arm · GitHub "

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2,173 Views
lizboxy
Contributor I

OK, It's all done,TKs!

But now,so how to change the Default Display to  dual MIPI DSI Panel?

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joanxie
NXP TechSupport
NXP TechSupport

as  I known, the default image "Image-imx8qmmek.bin" and dtb file "fsl-imx8qm-mek.dtb" support this already

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2,173 Views
lizboxy
Contributor I

I am using the BSP Linux 4.19.35_1.1.0 which I compile in yocto

I have changed DSI phy/DSI bridge status from “disable” to “okay”, but did’t work.

How can I port My DSI panel driver? My DSI Panel is dual mipi-DSI panel.

mipi_dsi_phy1: dsi_phy@56228300 {

                   #address-cells = <1>;

                   #size-cells = <0>;

                   compatible = "mixel,imx8qm-mipi-dsi-phy";

                   reg = <0x0 0x56228300 0x0 0x100>;

                   power-domains = <&pd_mipi0>;

                   #phy-cells = <0>;

                   /*status = "disabled";*/

                   status = "okay";

         };

 

         mipi_dsi1: mipi_dsi@56228000 {

                   compatible = "fsl,imx8qm-mipi-dsi";

                   clocks =

                            <&clk IMX8QM_MIPI0_PXL_CLK>,

                            <&clk IMX8QM_MIPI0_BYPASS_CLK>,

                            <&clk IMX8QM_MIPI0_DSI_PHY_CLK>;

                   clock-names = "pixel", "bypass", "phy_ref";

                   power-domains = <&pd_mipi0>;

                   csr = <&mipi_dsi_csr1>;

                   phys = <&mipi_dsi_phy1>;

                   phy-names = "dphy";

                   pwr-delay = <100>;

                   /*status = "disabled";*/

                   status = "okay";

                   port@0 {

                            mipi_dsi1_in: endpoint {

                                     remote-endpoint = <&dpu1_disp0_mipi_dsi>;

                            };

                   };

 

                   port@1 {

                            mipi_dsi1_out: endpoint {

                                     remote-endpoint = <&mipi_dsi_bridge1_in>;

                            };

                   };

         };

 

         mipi_dsi_bridge1: mipi_dsi_bridge@56228000 {

                   #address-cells = <1>;

                   #size-cells = <0>;

                   compatible = "nwl,mipi-dsi";

                   reg = <0x0 0x56228000 0x0 0x300>;

                   interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;

                   interrupt-parent = <&irqsteer_dsi0>;

                   clocks =

                            <&clk IMX8QM_MIPI0_BYPASS_CLK>,

                            <&clk IMX8QM_MIPI0_DSI_TX_ESC_CLK>,

                            <&clk IMX8QM_MIPI0_DSI_RX_ESC_CLK>;

                   clock-names = "phy_ref", "tx_esc", "rx_esc";

                   assigned-clocks = <&clk IMX8QM_MIPI0_DSI_TX_ESC_DIV>,

                                       <&clk IMX8QM_MIPI0_DSI_RX_ESC_DIV>;

                   assigned-clock-rates = <18000000>, <72000000>;

                   power-domains = <&pd_mipi0>;

                   phys = <&mipi_dsi_phy1>;

                   phy-names = "dphy";

                   /*status = "disabled";*/

                   status = "okay";

                   port@0 {

                            mipi_dsi_bridge1_in: endpoint {

                                     remote-endpoint = <&mipi_dsi1_out>;

                            };

                   };

         };

THX

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2,173 Views
joanxie
NXP TechSupport
NXP TechSupport

 what do you mean dual mipi-DSI panel? do you need to use two panels? or one panel has dual channel? if you need to support two mipi dsi panel, as I mentioned before, you don't need to change dts, the default image supports this already

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2,173 Views
lizboxy
Contributor I

由于屏比较大,所以选了Dual-Mipi屏来显示,现在Driver应该OK了,可以显示了,但两个MIPI通道在一个屏上显示两个一样的图像,我理解这个现象应该是两个MIPI口的输出都是独立的,好像没有做内部切割和拼接的驱动吧?

但开机logo如何处理? 

目前有看到RK3399/MTK都有选这种Dual-Mipi屏,而且其驱动也应该写好的Driver,可以直接输出在一个大屏显示;MTK的Dual-MIPI的显示是在mipi_dsi_bridge里定义,i.MX8QM是否有对应drvier,是否在nwl,mipi-dsi里定义?

最后还有按照ModeText工具有测试:从结果上讲,屏的左右两边可以输出显示两个不同的图像,所以请帮忙看看如何解决logo的整屏显示,还有实时动态图像如何处理?还是必须把两个图像通过视频处理切割后再通过两个独立的MIPI拼接起来显示?谢谢!

Run modetest -M imx-drm -s 146:1536x2048-25 -s 148:1536x2048-25 ,Screen show picture as left.

Run modetest -M imx-drm -s 146:1536x2048-25, Screen show picture as right.

 

root@imx8qmmek:~# modetest -M imx-drm -s 146:1536x2048-25 -s 148:1536x2048-25
setting mode 1536x2048-25Hz@XR24 on connectors 146, crtc 36
failed to set gamma: Function not implemented
setting mode 1536x2048-25Hz@XR24 on connectors 148, crtc 94
failed to set gamma: Function not implemented

 

root@imx8qmmek:~# modetest -M imx-drm -s 146:1536x2048-25
setting mode 1536x2048-25Hz@XR24 on connectors 146, crtc 36
failed to set gamma: Function not implemented
Dual-MIPI ModeTest.png

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