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test tw9992 video decoder by mx8_v4l2_cap_drm

Question asked by Simon Lin on Apr 23, 2020
Latest reply on Apr 27, 2020 by Joan Xie

Hi 

 

I test test tw9992 video decoder by mx8_v4l2_cap_drm in below case

./mx8_v4l2_cap_drm -cam 1 -d "/dev/video1" -fmt YUYV -of

 

It create a YUYV raw data, I check it by vooya tool in ubuntu environment

There are two field on the screen

 

I take this for reference, then try to set deinterlace_mode in dts 

ISL79987 and adv7180 de-interlace driver for iMX8QXP boards 

 

 

&isi_4 {

+       deinterlace_mode = <2>;         /* 0 ~ 1: No de-interlacing,

+                                      2: Odd even weave, 3: Even odd weave

+                                      4: Odd even blending, 5: Even odd blending

+                                      6 ~ 7: Line doubling */

+       status = "okay";

};

 

Finally, I found it stuck in this case

ret = ioctl(fd, VIDIOC_DQBUF, &buf);

 

I dump MIPI CSI register as below, you can also check it in log file as attachment

Can you provide some suggestions?

 

[ 41.261982] ISI CHNLC register dump, isi4
[ 41.266001] CHNL_CTRL 0x0h = 0xe0ff0003
[ 41.271056] CHNL_IMG_CTRL 0x4h = 0x20002001
[ 41.276119] CHNL_OUT_BUF_CTRL 0x8h = 0x c000
[ 41.281178] CHNL_IMG_CFG 0xCh = 0x f002d0
[ 41.286238] CHNL_IER 0x10h = 0x3dff0000
[ 41.291301] CHNL_STS 0x14h = 0x 200
[ 41.296360] CHNL_SCALE_FACTOR 0x18h = 0x10001000
[ 41.301414] CHNL_SCALE_OFFSET 0x1Ch = 0x 0
[ 41.306512] CHNL_CROP_ULC 0x20h = 0x 0
[ 41.311580] CHNL_CROP_LRC 0x24h = 0x 0
[ 41.316718] CHNL_CSC_COEFF0 0x28h = 0x 0
[ 41.321777] CHNL_CSC_COEFF1 0x2Ch = 0x 0
[ 41.326884] CHNL_CSC_COEFF2 0x30h = 0x 0
[ 41.331946] CHNL_CSC_COEFF3 0x34h = 0x 0
[ 41.337039] CHNL_CSC_COEFF4 0x38h = 0x 0
[ 41.342100] CHNL_CSC_COEFF5 0x3Ch = 0x 0
[ 41.347160] CHNL_ROI_0_ALPHA 0x40h = 0x 0
[ 41.352666] CHNL_ROI_0_ULC 0x44h = 0x 0
[ 41.357785] CHNL_ROI_0_LRC 0x48h = 0x 0
[ 41.362840] CHNL_ROI_1_ALPHA 0x4Ch = 0x 0
[ 41.368167] CHNL_ROI_1_ULC 0x50h = 0x 0
[ 41.373226] CHNL_ROI_1_LRC 0x54h = 0x 0
[ 41.378590] CHNL_ROI_2_ALPHA 0x58h = 0x 0
[ 41.383649] CHNL_ROI_2_ULC 0x5Ch = 0x 0
[ 41.388707] CHNL_ROI_2_LRC 0x60h = 0x 0
[ 41.393759] CHNL_ROI_3_ALPHA 0x64h = 0x 0
[ 41.398822] CHNL_ROI_3_ULC 0x68h = 0x 0
[ 41.404154] CHNL_ROI_3_LRC 0x6Ch = 0x 0
[ 41.409244] CHNL_OUT_BUF1_ADDR_Y 0x70h = 0xbf600000
[ 41.414311] CHNL_OUT_BUF1_ADDR_U 0x74h = 0x 0
[ 41.419450] CHNL_OUT_BUF1_ADDR_V 0x78h = 0x 0
[ 41.424511] CHNL_OUT_BUF_PITCH 0x7Ch = 0x 5a0
[ 41.429631] CHNL_IN_BUF_ADDR 0x80h = 0x 0
[ 41.434688] CHNL_IN_BUF_PITCH 0x84h = 0x 0
[ 41.439796] CHNL_MEM_RD_CTRL 0x88h = 0x 0
[ 41.444855] CHNL_OUT_BUF2_ADDR_Y 0x8Ch = 0xbf300000
[ 41.449968] CHNL_OUT_BUF2_ADDR_U 0x90h = 0x 0
[ 41.455028] CHNL_OUT_BUF2_ADDR_V 0x94h = 0x 0

 

[ 43.462300] MIPI CSI2 HC register dump, mipi csi1
[ 43.467012] MIPI CSI2 HC num of lanes 0x100 = 0x0
[ 43.467017] MIPI CSI2 HC dis lanes 0x104 = 0xe
[ 43.478865] MIPI CSI2 HC BIT ERR 0x108 = 0x0
[ 43.478867] MIPI CSI2 HC IRQ STATUS 0x10C = 0x8
[ 43.478869] MIPI CSI2 HC IRQ MASK 0x110 = 0x1ff
[ 43.478870] MIPI CSI2 HC ULPS STATUS 0x114 = 0x0
[ 43.478872] MIPI CSI2 HC DPHY ErrSotHS 0x118 = 0x0
[ 43.478874] MIPI CSI2 HC DPHY ErrSotSync 0x11c = 0x0
[ 43.478879] MIPI CSI2 HC DPHY ErrEsc 0x120 = 0x0
[ 43.478888] MIPI CSI2 HC DPHY ErrSyncEsc 0x124 = 0x0
[ 43.571239] MIPI CSI2 HC DPHY ErrControl 0x128 = 0x0
[ 43.576300] MIPI CSI2 HC DISABLE_PAYLOAD 0x12C = 0x0
[ 43.581350] MIPI CSI2 HC DISABLE_PAYLOAD 0x130 = 0x0
[ 43.586410] MIPI CSI2 HC IGNORE_VC 0x180 = 0x0
[ 43.591462] MIPI CSI2 HC VID_VC 0x184 = 0x0
[ 43.596522] MIPI CSI2 HC FIFO_SEND_LEVEL 0x188 = 0x0
[ 43.601575] MIPI CSI2 HC VID_VSYNC 0x18C = 0x0
[ 43.606633] MIPI CSI2 HC VID_SYNC_FP 0x190 = 0x0
[ 43.611686] MIPI CSI2 HC VID_HSYNC 0x194 = 0x0
[ 43.616753] MIPI CSI2 HC VID_HSYNC_BP 0x198 = 0x0

 

[ 43.621816] MIPI CSI2 CSR register dump
[ 43.625672] MIPI CSI2 CSR PLM_CTRL 0x000 = 0x801
[ 43.630911] MIPI CSI2 CSR PHY_CTRL 0x004 = 0x2000af
[ 43.636404] MIPI CSI2 CSR PHY_Status 0x008 = 0x1
[ 43.641465] MIPI CSI2 CSR PHY_Test_Status 0x010 = 0x0
[ 43.646519] MIPI CSI2 CSR PHY_Test_Status 0x014 = 0x0
[ 43.651575] MIPI CSI2 CSR PHY_Test_Status 0x018 = 0x0
[ 43.656627] MIPI CSI2 CSR PHY_Test_Status 0x01C = 0x0
[ 43.661688] MIPI CSI2 CSR PHY_Test_Status 0x020 = 0x0
[ 43.666739] MIPI CSI2 CSR VC Interlaced 0x030 = 0x0
[ 43.671799] MIPI CSI2 CSR Data Type Dis 0x038 = 0x0
[ 43.676850] MIPI CSI2 CSR 420 1st type 0x040 = 0x0
[ 43.681911] MIPI CSI2 CSR Ctr_Ck_Rst_Ctr 0x044 = 0x1
[ 43.686963] MIPI CSI2 CSR Stream Fencing 0x048 = 0x0
[ 43.692020] MIPI CSI2 CSR Stream Fencing 0x04C = 0x0

 

Thanks

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