With i.MX 8M (or i.MX 8X), can the RX and TX buffer descriptors (BD) used by the ENET Ethernet device be cacheable? Same question for the buffers pointed to by the BD?
That could enhance SW performance. If they can be cacheable, it means that the ENET is aware of a change made by Cortex-A53 (or Cortex-A35) core to the BD in DDR by automatic HW cache coherency mechanism? (snooping)