I have been looking at the ""documentation"" for OCRAM in the IMX6ULL ref manual.
It seems to have mysterious 'advanced features' designed to avoid timing issues..
These advanced features are controlled by IOMUXC.GPR3 and configure wait states and pipe lining. It seems that at 'higher frequency' these features are required to avoid potential timing problems.
What are these potential timing problems?? Does the read / write fail or lock up or does that chip just explode?
What exactly is 'higher frequency'? When should wait states and pipe lining be enabled?
I have checked the ref manuals for many IMX6 devices and they contain the same cut-and-paste info.