I am trying to use PLL3 PFD3 clock as the source for the eSDHC1 clock. The problem is getting the PLL3 PFD3 functional. I am doing the following:
- Check ANADIG_PLL3_LOCK to verify that PLL3 is running and locked
- Enable PLL3 PFD3 by setting CCM_CCSR_PLL3_PFD3_EN high (see SDHC Clock Enable.png)
- Check that PDF3_CLKGATE bit in ANADIG_PLL3_PFD is low (which if I'm reading the RM correctly means that PLL3_PFD3 is enabled). Also the PLL3_PFD3 bit in CCM_CPPDSR is low meaning the output is enabled.
- However when I select PLL3_PFD3 as the clock source for ESDHC1 in CM_CSCMR1 (line in yellow), CCM_CCSR_PLL3_PFD3_EN goes low which means the PLL3 PFD3 is no longer functional. This is verified by SDHC1_PRSSTAT_SDSTB being low indicating no input clock.
What am I missing to get PLL3 PFD3 functional as the eSDHC1 clock?