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P2020 Processor GPCM with DLL Bypass Read/Write Timing

Question asked by guobin lu on Apr 16, 2020
Latest reply on Apr 27, 2020 by ufedor

When looking at the P2020 QorIQ Integrated Processor Reference Manual (Rev. 2, 12/2012), I notice that when the local bus is in bypass mode, eLBC drives new address, data, and control signals effectively on falling edges of LCLK, but continues to sample synchronous read data on rising edges of LCLK to maximize the set-up margin for reads. However, the precise timing relationship between TA signal and read-write signal is not clearly stated.
I need to do an accurate timing analysis, but I don't know the specific timing relationship between TA signal and read-write signal, and which rising edge of LCLK is the sampling point for reading data when TA signal is asserted.
The register settings in my design are as follows:



Any help would be much appreciated.