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S9KEAZN64AMLC Failure of double-edge sampling measurement period

Question asked by zhiyong zhang on Apr 14, 2020
Latest reply on May 6, 2020 by Kerry Zhou

Double Edge sampling using FTM2(CH2&CH3) of S9KEAZN64AMLC , sample the period of  pwm signal .

When the duty cycle is greater than 95%,The measurements are incorrect.("20KHz" has been misidentified as "10KHz ").

Can the IC measure the period of a signal with a duty cycle greater than 95% ? If it can be collected, what should we pay attention to when designing?

 

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