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imx6dl SPI timing issue

Question asked by Nanao Akimichi on Apr 13, 2020
Latest reply on Apr 30, 2020 by igorpadykov

Dear all,

 

I'm using following kind of Kernel ver. with i.MX6DL.

https://github.com/Freescale/linux-fslc/tree/4.14-1.0.x-imx

 

I'm facing SPI communication problem.

At the first packet of SPI communication,  SPI_CLK become High↑  after CS becomes Low ↓.
That's why the MSB bit always becomes "1". 

 

Send data "14 00 00 10 FF" -> 0b1 + 0x14 + 0x00 + ... -> Receive data "8A 00 00 08 7F"

Fig.1: Sending data "14 00 00 10 FF"  becomes "8A 00 00 08 7F" because of the first clk ↑

 

 

With another CS device , we can see same phenomenon for the first packet.

Send data "00 00 xx" -> 0b1 + 0x00 + 0x00 -> Receive data "80 00 xx"

Fig. 2: Sending data "00 00 xx"  becomes "80 00 xx" because of the first clk ↑

 

 

For the same device, there is no problem from 2nd packet as long as I checked.

But I don't know the root cause of this phenomenon, and when this problem happen.

 

In my environment, there is no EVK board, so this problem can be seen only with my own board with SPI1_cs1, cs2, cs3, SPI2_cs2.

 

Is there any way to avoid this problem?

 

Best regards,

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