we are currently designing the SJA1105QEL Scheme, please help us to see if the attached scheme is feasible, thank you
I think it will be functional. However we typically recommend that clock signals were designed in point-to-point topology. This is done in your scheme for all PHYs, however not for switches. I believe a clock distribution device would be also helpful there.
Hello, I have the following problem with my SOC docking with SJA1105Q: 1, the SPI of the SOC supports up to 24.75 Mhz, can I configure the SJA1105Q with frequencies below 25 Mhz?2,SOC only supports 16 bit SPI mode, how to configure with Sja1105q?
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