My customer is trying to maximize the throughput of the processor, by minimizing the clock's divisions.
please find his inquires below:
1) My specific question is: how to change the CLK_OSC32M_DIV register from its default value of 1 to 0: from 16 Mhz to 32 Mhz.
What I am trying to do is:
Which results in a runtime error.
2) Additionally, if you could spot some more clock division settings that I am missing, I would appreciate it.
I couldn't attach his project but he used GPIO Driver example code from the QN9080 SDK.
Please advise back and stay safe.
Thanks and regards,