AnsweredAssumed Answered

What does a Master ID of 0x0 for all AHB Prefetch Buffers do?

Question asked by Stefan Mitterhauser on Apr 2, 2020
Latest reply on May 13, 2020 by Stefan Mitterhauser

Hello,

the RT1020 flexspi_nor_polling_transfer demo project calls the function flexspi_nor_flash_init which gets the default config for flexspi and initializes most of the FlexSPI with default parameters.

The function GetDefaultConfig sets the Master IDs for all prefetch buffers to 0x0 because of the memset calls.

 

The RT1020 Reference Manual specifies in a note on page 1515

but I think that is exactly what the demo project/FLEXSPI_GetDefaultConfig function is doing.

 

  1. Could this be the reason for the performance issues in this post Negative effect of enabling Prefetcher for XIP from NOR flash memory (jeremyzhou)? I have the same performance issue when I use one flash with lower addresses XIP and higher addresses data and no caches active. If I calculate a crc of the data area I assumed that the prefetch buffer will be emptied all the time because of switching between XIP read and data read and both don't fit in one AHB prefetch buffer but maybe it is due to the master id for all buffers being set to 0.
  2. I'm wondering what does a Master ID of 0x0 for all AHB Prefetch Buffers do? Is now no AHB Prefetch buffer active? Will it just use the first buffer and 2. and third buffer are a waste of buffer space? Will it switch between buffers?
  3. What happens if you use 1kByte for buffers 0 to 2, therefore buffer size for buffer[3] will be 0? Should you disable prefetch for buffer 3?
  4. Why does a AHB Cachable Read check the FlexSPI TX buffer and not the read buffer?

  5. If we do not use stop mode is there any negative impact if we still enable CLRAHBBUFOPT?

 

Kind regards,

Stefan

Outcomes