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How to disable some logic when the CPC is configured as SRAM on T4240

Question asked by 同想 蔡 on Apr 1, 2020
Latest reply on Apr 6, 2020 by ufedor

I have configured the CPC as SRAM on the T4240 ,

By design, cache block consists of fast cache memory and address associative logic, this logic continuously monitoring bus transactions and perform necessary actions, if any particular memory access hits cache line.


When the cache is configured as SRAM, this associative logic as still active and may consume SRAM memory bandwidth and/or add some random latency to SRAM memory accesses.


The information on how to disable this logic is not specified in our public documentation, how to disable this logic?