How to generate 5 injection pulses using eTPU's QOM mode

[709458227]

I want to produce five pulses, but no matter how you debug them, I only produce one pulse.

I'm using the code in the following example.

How can I change this code to achieve the effect I want?

/**************************************************************************
* FILE NAME: $RCSfile: qom_example2.c,v $ COPYRIGHT (c) FREESCALE 2004 *
* DESCRIPTION: All Rights Reserved *
* This is a sample MPC5500 program to show a more complex use of the *
* eTPU QOM function. *
*========================================================================*
* ORIGINAL AUTHOR: Geoff Emerson (r47354) *
* $Log: qom_example2.c,v $
* Revision 1.3 2004/12/02 15:22:58 r47354
* Added #include "mpc5554_vars.h"
*
* Revision 1.2 2004/11/11 14:29:49 r47354
* Tidy up and formatting.
*
* Revision 1.1 2004/11/09 11:17:41 r47354
* No changes to code, just updated for CVS and checked into CVS.
*........................................................................*
* 0.1 G.Emerson 28/Apr/04 Initial version. *
* 0.2 Updated for new build structure. *
* 0.3 G.Emerson 25/June/04 Add FS_ to macros *
* 0.4 G.Emerson 16/July/04 Demonstrate TEST running across engines*
* 0.5 G.Emerson 28/Oct/04 Fix interrupt bit clearing *
* Fix include paths *
**************************************************************************/

#include "mpc5554.h" /* mpc5554 register definitions */
#include "etpu_util.h" /* Utility routines for working with eTPU */
#include "fs_gpio.h" /* GPIO API for the MPC5500 family*/
#include "etpu_set1.h" /* eTPU standard function set 1 */
#include "etpu_qom.h" /* eTPU QOM API */

#include "mpc5554_vars.h"

#include "etpu_test.h" /*eTPU TEST API */

/* User written include files */
#include "qom_example2.h" /*include application specific defines. */

#define ETPU_OUTPUT_PAD_CONFIG FS_GPIO_PRIMARY_FUNCTION + \
FS_GPIO_MAXIMUM_SLEW_RATE + \
FS_GPIO_OUTPUT_DRAIN_DISABLE + \
FS_GPIO_READBACK_ENABLE + \
FS_GPIO_OUTPUT_BUFFER_ENABLE

union etpu_events_array my_QOM_event_arrayA[QOM_arrayA_size];
union etpu_events_array my_QOM_event_arrayB[QOM_arrayB_size];
union etpu_events_array my_QOM_event_arrayC[QOM_arrayC_size];

union etpu_events_array my_QOM_event_arrayA[QOM_arrayA_size] =
{ (0x010000 << 1) + FS_ETPU_PIN_HIGH,
(0x008000 << 1) + FS_ETPU_PIN_LOW,
(0x004000 << 1) + FS_ETPU_PIN_HIGH,
(0x002000 << 1) + FS_ETPU_PIN_LOW,
(0x010000 << 1) + FS_ETPU_PIN_HIGH,
(0x010000 << 1) + FS_ETPU_PIN_LOW,
(0x010000 << 1) + FS_ETPU_PIN_HIGH
};

union etpu_events_array my_QOM_event_arrayB[QOM_arrayB_size] =
{ (0x010000 << 1) + FS_ETPU_PIN_LOW,
(0x008000 << 1) + FS_ETPU_PIN_HIGH,
(0x004000 << 1) + FS_ETPU_PIN_LOW,
(0x002000 << 1) + FS_ETPU_PIN_HIGH,
(0x010000 << 1) + FS_ETPU_PIN_LOW,
(0x010000 << 1) + FS_ETPU_PIN_HIGH,
(0x010000 << 1) + FS_ETPU_PIN_LOW
};

union etpu_events_array my_QOM_event_arrayC[QOM_arrayC_size] =
{ (0x010000 << 1) + FS_ETPU_PIN_LOW,
(0x010000 << 1) + FS_ETPU_PIN_HIGH,
(0x010000 << 1) + FS_ETPU_PIN_LOW,
(0x010000 << 1) + FS_ETPU_PIN_HIGH,
(0x010000 << 1) + FS_ETPU_PIN_LOW,
(0x010000 << 1) + FS_ETPU_PIN_HIGH,
(0x010000 << 1) + FS_ETPU_PIN_LOW
};

int32_t init_error; /*initialization error code. */
uint32_t *fs_free_param;

main ()
{
uint8_t chan;
uint32_t *QOM0_ram_ptr, *QOM0_last_match_ptr;
int32_t error_code;
int32_t x10, y10; /*these are used to generate a delay*/
vuint16_t *upper_SCR16;
vuint32_t *upper_SCR32;

FMPLL.SYNCR.R = 0x06000000; /* MFD = 0b110, RFD=0b000, 8MHz*16=128MHz */

/* initialize eTPU hardware */
fs_etpu_init (my_etpu_config, (uint32_t *) etpu_code, sizeof (etpu_code),
(uint32_t *) etpu_globals, sizeof (etpu_globals));

/* enable all timebases */
fs_timer_start ();

/*clear interrupt and DTR flags*/
for (chan = 0; chan < 63; chan++)
{
upper_SCR32 = &ETPU.CHAN[chan].SCR.R;
upper_SCR16 = (vuint16_t *) upper_SCR32;
*upper_SCR16 = 0xC0C0; /* clear DMA/interrupt service request */
fs_etpu_disable (chan); /*disable all channels */
}

/* configure the pins on the MPC5554 */
fs_gpio_config (FS_GPIO_ETPUA2, ETPU_OUTPUT_PAD_CONFIG);
fs_gpio_config (FS_GPIO_ETPUA4, ETPU_OUTPUT_PAD_CONFIG);
fs_gpio_config (FS_GPIO_ETPUA10, ETPU_OUTPUT_PAD_CONFIG);
fs_gpio_config (FS_GPIO_ETPUA16, ETPU_OUTPUT_PAD_CONFIG);
fs_gpio_config (FS_GPIO_ETPUA22, ETPU_OUTPUT_PAD_CONFIG);
fs_gpio_config (FS_GPIO_ETPUA28, ETPU_OUTPUT_PAD_CONFIG);

error_code =
fs_etpu_qom_init (QOM0,
FS_ETPU_PRIORITY_MIDDLE,
FS_ETPU_QOM_SINGLE_SHOT,
FS_ETPU_TCR1,
FS_ETPU_QOM_INIT_PIN_LOW,
FS_ETPU_QOM_IMMEDIATE,
(uint32_t *) 0,
0,
QOM_arrayA_size,
my_QOM_event_arrayA);
if (error_code != 0)
return (QOM0 + 1);

while (ETPU.CHAN[QOM0].SCR.B.CIS == 0)
{
/*wait for QOM0 to finish */
/*WARNING: Endless loop is possible */
}

QOM0_ram_ptr = fs_etpu_data_ram (QOM0);
QOM0_last_match_ptr =
(uint32_t *) ((uint32_t) QOM0_ram_ptr - (uint32_t) & ETPU_DATA_RAM +
FS_ETPU_QOM_LAST_MATCH_TIME_OFFSET);

for (x10 = 1; x10 < 20000; x10++)
{
y10 = x10 + 2;
y10 = x10 - 2;
} /* add delay to demonstrate immediate versus ref_addr */

error_code =
fs_etpu_qom_init (QOM2,
FS_ETPU_PRIORITY_MIDDLE,
FS_ETPU_QOM_CONTINUOUS_A,
FS_ETPU_TCR1,
FS_ETPU_QOM_INIT_PIN_HIGH,
FS_ETPU_QOM_IMMEDIATE,
(uint32_t *) 0,
0,
QOM_arrayB_size,
my_QOM_event_arrayB);
if (error_code != 0)
return (QOM2 + 1);

error_code =
fs_etpu_qom_init (QOM1,
FS_ETPU_PRIORITY_MIDDLE,
FS_ETPU_QOM_SINGLE_SHOT,
FS_ETPU_TCR1,
FS_ETPU_QOM_INIT_PIN_HIGH,
FS_ETPU_QOM_USE_REF_ADDRESS,
QOM0_last_match_ptr,
0,
QOM_arrayB_size,
my_QOM_event_arrayB);
if (error_code != 0)
return (QOM1 + 1);

/*initialise QOM3 to recieve a link*/
error_code =
fs_etpu_qom_init (QOM3,
FS_ETPU_PRIORITY_MIDDLE,
FS_ETPU_QOM_SINGLE_SHOT,
FS_ETPU_TCR1,
FS_ETPU_QOM_INIT_PIN_HIGH_LINK,
FS_ETPU_QOM_IMMEDIATE,
(uint32_t *) 0,
0,
QOM_arrayB_size,
my_QOM_event_arrayB);
if (error_code != 0)
return (QOM3 + 1);

/*initialise QOM4 to recieve a link*/

error_code =
fs_etpu_qom_init (QOM4,
FS_ETPU_PRIORITY_MIDDLE,
FS_ETPU_QOM_LOOP,
FS_ETPU_TCR1,
FS_ETPU_QOM_INIT_PIN_LOW_LINK,
FS_ETPU_QOM_IMMEDIATE,
(uint32_t *) 0,
2, /* number of loops */
QOM_arrayB_size,
my_QOM_event_arrayB);
if (error_code != 0)
return (QOM4 + 1);

error_code =
fs_etpu_qom_init (QOM5,
FS_ETPU_PRIORITY_MIDDLE,
FS_ETPU_QOM_CONTINUOUS,
FS_ETPU_TCR1,
FS_ETPU_QOM_INIT_PIN_NO_CHANGE_LINK,
FS_ETPU_QOM_IMMEDIATE,
(uint32_t *) 0,
0,
QOM_arrayB_size,
my_QOM_event_arrayB);
if (error_code != 0)
return (QOM5 + 1);

/* now send link to channel QOM3 ; wait for it to finish then do new pulse
stream relative to last match*/
fs_etpu_test (TEST0 + 64 + 128, QOM3, FS_ETPU_TEST_GENERATE_LINK);
while (ETPU.CHAN[QOM3].SCR.B.CIS == 0)
{
/*wait for QOM3 to finish */
/*WARNING: Endless loop is possible */
}

error_code =
fs_etpu_qom_init (QOM3,
FS_ETPU_PRIORITY_MIDDLE,
FS_ETPU_QOM_SINGLE_SHOT,
FS_ETPU_TCR1,
FS_ETPU_QOM_INIT_PIN_NO_CHANGE,
FS_ETPU_QOM_USE_LAST_EVENT,
(uint32_t *) 0,
0,
QOM_arrayC_size,
my_QOM_event_arrayC);

for (x10 = 1; x10 < 80000; x10++)
{
y10 = x10 + 2;
y10 = x10 - 2;
} /* add delay
/* now send link to channel QOM4/5 */
fs_etpu_test (TEST0 + 64 + 128, QOM4, FS_ETPU_TEST_GENERATE_LINK);

fs_etpu_test (TEST0 + 64 + 128, QOM5, FS_ETPU_TEST_GENERATE_LINK);

/* now send link to channel QOM4/5 before it has completed
(test LSR_flag functionality)*/
for (x10 = 1; x10 < 80000; x10++)
{
y10 = x10 + 2;
y10 = x10 - 2;
}
fs_etpu_test (TEST0 + 64 + 128, QOM4, FS_ETPU_TEST_GENERATE_LINK);

fs_etpu_test (TEST0 + 64 + 128, QOM5, FS_ETPU_TEST_GENERATE_LINK);

/*wait until QOM4 has fininshed then try sending another link - nothing
should happen due to LSR_flag functionality.*/
while (ETPU.CHAN[QOM4].SCR.B.CIS == 0)
{
/*wait for QOM4 to finish */
/*WARNING: Endless loop is possible */
}
fs_etpu_test (TEST0 + 64 + 128, QOM4, FS_ETPU_TEST_GENERATE_LINK);

for (;;); /*Foo. */

}

/*********************************************************************
*
* Copyright:
* Freescale Semiconductor, INC. All Rights Reserved.
* You are hereby granted a copyright license to use, modify, and
* distribute the SOFTWARE so long as this entire notice is
* retained without alteration in any modified and/or redistributed
* versions, and that such modified versions are clearly identified
* as such. No licenses are granted by implication, estoppel or
* otherwise under any patents or trademarks of Freescale
* Semiconductor, Inc. This software is provided on an "AS IS"
* basis and without warranty.
*
* To the maximum extent permitted by applicable law, Freescale
* Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
* INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A
* PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH
* REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF)
* AND ANY ACCOMPANYING WRITTEN MATERIALS.
*
* To the maximum extent permitted by applicable law, IN NO EVENT
* SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER
* (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS,
* BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER
* PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
*
* Freescale Semiconductor assumes no responsibility for the
* maintenance and support of this software
********************************************************************/

[davidtosenovjan]

Which device you are using?