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about Internal POR

Question asked by on Mar 31, 2020
Latest reply on Mar 31, 2020 by Yuri Muhin



I was able to find a description of the state where the reset was released.
Please tell me the VDD_ARM voltage and VDD_SOC voltage that is reset or reset is released.


Excerpt from section 6.2.5 of i.MX 7Dual Applications Processor Reference Manual

• 4ms after the external power supply VDDHIGH_IN is valid
• 1ms after the VDD_SOC_CAP supply is valid


best regards