We have developed a board using the iMX6 Solo and our own discrete power supplies. The board is running great but we have one final point of concern before running production.
We have an external reset generator attached to POR_B which is also wired to another microcontroller so it can also generate a reset to the iMX6.
The reset generator is open-collector and because POR_B is on the SNVS domain has a pull-up to this rail (3.3V).
The reset generator waits for the 1.35V ARM/SOC rail to rise up to 0.9V then waits 200ms before releasing reset. The hardware guide says we have to wait for ARM_CAP, SOC_CAP and PU_CAP to be stable before releasing POR_B. However these are all outputs from the internal LDOs so rather than monitor each we just delay a fixed amount when we know 1.35V has come up enough.
Anyway - our reset generator is open collector but during power up its output is not asserted until the 1.35V rail rises sufficiently. Because the POR_B pin has a pull-up to 3.3V there is a brief blip on 3.3V for 20ms or so before POR_B is asserted. See below (blue=POR_B, red = 1.35V):
The guides say to ensure POR_B is asserted immediately on power up and released once the _CAP rails are up. Will we have any issues with the above waveform on POR_B?
I have also seen advice stating that if not using POR_B it can be tied to VDD_SNVS (3.3V) anyway which is what we have briefly.
Our boards boot every time and reset when this line is asserted. I just want to make sure we won't have startup issues in future!