In the case of Internal POR, is the release timing of the reset inside the CPU when both VDD_ARM_IN and VDD_SOC_IN are supplied?
In the case of BOOT with QuadSPI (QSPI) flash, what is the delay time from the supply of both VDD_ARM_IN and VDD_SOC_IN to the start of access to flash?
Excerpt from i.MX 7Dual Applications Processor Reference Manual
188.8.131.52 Internal POR
If the external SRC_POR_B signal is not used (always held high or left unconnected), the processor defaults to the internal POR function (PMU controls generation of the POR based on the power supplies).
If the internal POR function is used, the following power supply requirements must be met:
• VDD_ARM_IN and VDD_SOC_IN may be supplied from the same source, or
• VDD_SOC_IN can be supplied before VDD_ARM_IN with a maximum delay of 1ms.