We've built a board which uses 2 16Gb twin die Micron DDR4 ICs connected in a single rank with 2 clocks to a i.MX8M. The board fails it's training as follows using the Mscale DDR tool v3.10:
Downloading file 'bin\ddr4_train1d_string.bin' ..Done
Downloading file 'bin\ddr4_train2d_string.bin' ..Done
Downloading file 'bin\ddr4_imem_1d.bin' ..Done
Downloading file 'bin\ddr4_dmem_1d.bin' ..Done
Downloading file 'bin\ddr4_imem_2d.bin' ..Done
Downloading file 'bin\ddr4_dmem_2d.bin' ..Done
Downloading IVT header...Done
Downloading file 'bin\m850_ddr_stress_test.bin' ...Done
Download is complete
Waiting for the target board boot...
PF0100 is not found: ID=0x0
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MX8 DDR Stress Test V3.10
Built on Feb 5 2020 14:08:44
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--Set up the MMU and enable I and D cache--
- This is the Cortex-A53 core
- Check if I cache is enabled
- Enabling I cache since it was disabled
- Push base address of TTB to TTBR0_EL3
- Config TCR_EL3
- Config MAIR_EL3
- Enable MMU
- Data Cache has been enabled
- Check system memory register, only for debug
- VMCR Check:
- ttbr0_el3: 0x91d000
- tcr_el3: 0x2051c
- mair_el3: 0x774400
- sctlr_el3: 0xc01815
- id_aa64mmfr0_el1: 0x1122
- MMU and cache setup complete
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ARM clock(CA53) rate: 800MHz
DDR Clock: 800MHz
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DDR configuration
DDR type is DDR4
Data width: 16, bank num: 16
For DDR4, bank num is the total of 4 bank groups and 4 banks per group
Row size: 16, col size: 10
One chip select is used
Number of DDR controllers used on the SoC: 1
Density per chip select: 2048MB
Density per controller is: 2048MB
Total density detected on the board is: 2048MB
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MX8M: Cortex-A53 is found
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============ Step 1: DDRPHY Training... ============
---DDR 1D-Training @800Mhz...
[Process] End of initialization
[Process] End of read enable training
[Process] End of fine write leveling
[Process] End of read DQ deskew training
[Process] End of MPR read delay center optimization
[Process] End of Write Leveling coarse delay
PMU: Error: Dbyte 0 lane 0 txDqDly passing region is too small (width = 0)
PMU: ***** Assertion Error - terminating *****
[Result] FAILED
WE have been in discussion with NXP through our distributor for months now but it seems that nobody really knows much about DDR4 memory. So we though it might be useful to throw it open to the community.
Attached is a copy of the RPA spreadsheet, the script file and the log as printed above.
Thank you in advance.
