LS1046A: DIFF_SYSCLK, Serdes Frequency

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LS1046A: DIFF_SYSCLK, Serdes Frequency

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maxime_guillot
Contributor III

Hello,

I develop a custom board with the LS1046A CPU.

 

I am using oscillator for DIFF_SYCLK and SerDes clocks.

Your specification for the clocks frequencies is not clear for me.

You specify a frequency of 100MHz with no minimum neither maximum except frequency tolerance of +/- 300ppm.

What does this mean?

Can I use any clock frequency as long as this clock is within +/-300ppm?

Is there any requirement on the clock frequency?

Can I use 25, 50, 125MHz, 156.25MHz for DIFF_SYCLK and SerDes clocks?

Thank you

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Bulat
NXP Employee
NXP Employee

Please treat tolerance of +/- 300ppm as allowed clock range specification. So minimum DIFF_SYCLK frequency is 100MHz - 300ppm, maximum frequency is 100MHz +300ppm.

Regards,

Bulat

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