I would like to improve my project.
If i have 4 x DDR3 chips on the same layer(top or bottom). From now i will call them "M" with a number.
May i crate an hybrid topology between T and fly-by using chip selects and multiple clocks?
M1-M2 use CLK0 diff signal, CS0 data D[0-31]
use CLK1,CS1 and data D[32-63].
May i do that or i'm forced to use only first 32bits(data)?
The address lines could divide in 2 between 2 memory group like the T topology, like they are routed between M2 and M3 and then split.
ck0 ||||addr ck1
|M1||M2| <=====> |M3||M4|