It is my understanding, per
S32K1XXRM rev 12.1 page 171 "This bit field [PDB_BB_SEL_2, PDB_BB_SEL_1] is ... Reserved and Read-Only Zero for S32K14x"
that only 8 ADC0 channels with PDB0 can be used in back to back mode for S32K144 and S32K146, thus option PDB_BB_SEL_2/SIMCHIPCTL=0
is not supported.
What is then the alternative to use, considering throughput usage and responsiveness? Or (least preferred option) should the PCB be modified to use only 8 ADC0 channels and the remaining from ADC1?
Note: software trigger is selected as the trigger input source.