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IMX8M CSI-MIPI data rate settings - start of transmission error on high data rate

Question asked by Johannes Busch on Mar 17, 2020
Latest reply on Apr 4, 2020 by Joan Xie

Hello, I am developing a kernel driver for the OmniVision MIPI CSI camera OH02A10 on the IMX8M processor.

The driver works totally fine, but only if I configure the PLLs of the sensor to output a 360MHz MIPI PHY clock and 45MHz pixel clock, while the sensor normally runs on a 720MHz MIPI PHY clock and 90MHz pixel clock.

Therefore I can only achieve half of the data rate of the sensor, which is 1920x1080, 60fps,  10-bit raw over two lanes (I get 30fps instead).

I have double-checked the sensors registers of the reg settings I got from OmniVision for 720MHz mode, so the sensor should be fine.

 

When I try to stream with 720MHz, I get the ErrSotSync and ErrSotHs registers. (start of transmission error)

I am trying to debug this but it is hard to find any information I can relate on because the IMX8M Reference Manual has this part still missing and it's not clear which Reference Manual I can adapt.

 

I tried different HS_settle values, which I got from this thread: Explenation for HS-SETTLE  parameter in MIPI CSI D-PHY registers .

 

If you scroll down there is a table posted from an NXP colleague saying it should be used for IMX8M hs_settle calculation, but it confuses me, that it does not relate to drivers/media/platform/imx8/mxc-mipi-csi2_yav.c which is used for imx8m, right? In the file, the HS_settle value increases with higher data rate, but not in the table.

 

So my questions are, what do I have to configure to get a high data rate on IMX8M CSI-MIPI except for HS_settle? On what HS_settle information can I relate to? Where does the table come from? On which reference manual can I relate to, since it seems to be a mixture of iMX7D and iMX6sll? (see this thread iMX8M MIPI-CSI 4-lane configuration )


Do I have to change anything on these clock configurations? What are they for?

clocks = <&clk IMX8MQ_CLK_DUMMY>,
      <&clk IMX8MQ_CLK_CSI1_CORE>,
      <&clk IMX8MQ_CLK_CSI1_ESC>,
      <&clk IMX8MQ_CLK_CSI1_PHY_REF>;
clock-names = "clk_apb", "clk_core", "clk_esc", "clk_pxl";
assigned-clocks = <&clk IMX8MQ_CLK_CSI1_CORE>,
        <&clk IMX8MQ_CLK_CSI1_PHY_REF>,
        <&clk IMX8MQ_CLK_CSI1_ESC>;
assigned-clock-rates = <133000000>, <100000000>, <66000000>;

 

 

Also, the MIPI PHY clock is DDR-mode right? Does that mean when the PLLs on the sensor are set to 720MHz I can stream with 1440Mbps/lane? But then 1920x1080x60fpsx10bit =  1,244,160,000Mbps should be doable with one lane? Or do I have to calculate with 16-bit for that?

 

Also, there is this "fsl,two-8bit-sensor-mode;" option which says should be turned on, when using two 8-bit camera or 16-bit camera. Does this also relate to 10bit camera?

 

Best regards,

Johannes

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