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Questions about DDR3 configuration details, iMX6DL

Question asked by Jari Peltonen on Mar 4, 2020
Latest reply on Mar 26, 2020 by Jari Peltonen


I am working on SW for a product that is based on iMX6 Dual Lite processor.
SDRAM clock frequency is 400MHz (clock cycle 2.5ns).
We are planning to change SDRAM to a bigger one and one candidate for the new SDRAM is a DDR3-1866 (-107) component.


Timing values for this SDRAM are; tRC for it is 47.91ns, tRAS is 34ns and tFAW is 35ns (2KB page size).

MMDC configuration values would then be tRC=20CK, tRAS=14CK and tFAW=14CK, respectively.

Is this correct? Would these values work ok on our HW?


Best regards,