I would greatly appreciate if someone who has one of these chips up and running can confirm the following:
* VSSPLL, VSSA and GND are all connected together in a star fashion. I think that is what the EVB/DEMO board schematics are trying to indicate.
I notice that VDDA and VRH are connected together on the demo boards. Are you seeing noise or is the ADC pretty clean? Or are you filtering the power going into VRH?