The docs for the FlexSPI controller say that the output SPI clock is turned off when the interface is idle. Timing diagrams, though, show the clock continuing off the right edge of the picture after the end of a transaction.
How many additional clock cycles (if any) can I be guaranteed to get after the transaction is over? I'm interfacing to an FPGA with no PLL so I'll need those clocks.
Example timing diagram from page 1642 of the i.MX RT1060 Reference Manual: