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iMX Clock Divider

Question asked by Raajesh Kotteeswaran on Feb 27, 2020
Latest reply on Mar 25, 2020 by igorpadykov

I am trying to divide a clock (CLKO2) to 12MHz from its default value 24MHz. From imx6qclk.c there is function call to 

clk[IMX6QDL_CLK_CKO2_PODF]  = imx_clk_divider("cko2_podf", "cko2_sel", base + 0x60, 21, 3);

whatever i change in the bit values (3/4/5 ) the divider is still the same. can someone explain how this clock divider works. Thanks